The present invention relates to a method of making a semiconductor device in which an impurity is doped for improvement of contact to electrode.
When electrode wiring lines are connected to source and drain regions in a MOSFET, contact resistance at an interface between an electrode and a source and at an interface between an electrode and a drain must be decreased. To this end, an impurity is newly doped into source and drain surfaces to make them highly-concentrated impurity regions.
An impurity doping process employed in the production of an SRAM using a CMOS structure will be described hereunder.
Firstly, an n-channel MOSFET and a p-channel MOSFET are formed through an ordinary process. More particularly, as shown in FIG. 2A, a p-type well 32 is first formed in a predetermined region of a n-type semiconductor substrate 31 and a gate electrode 34 constituting the n-channel MOSFET is formed on the p-type well 32 through a gate oxide film 33. At another predetermined region of the semiconductor substrate 31, a gate electrode 35 constituting the p-channel MOSFET is formed through the gate oxide film 33. An n-channel MOSFET region and a p-channel MOSFET region are sectioned by a field oxide film 36.
Subsequently, n-type diffusion layers 37 serving as source and drain of the n-channel MOSFET and p-type diffusion layers 38 serving as source and drain of the p-channel MOSFET are formed. Further, in another region of the p-type well 32, an n-type diffusion layer 37a for body contact is formed.
Thereafter, as shown in FIG. 2B, an inter-layer insulating film 39 is formed on the semiconductor substrate 31, covering the gate electrodes 34 and 35 and the field oxide film 36. Subsequently, as shown in FIG. 2C, a contact hole 37b is formed in the inter-layer insulating film 39 to overlie the diffusion layer 37a. Then, as shown in FIG. 2D, a plug 40a made of polycrystal silicon doped with an impurity is embedded in the contact hole 37b and a GND wiring line 40b is connected to the plug 40a.
Next, as shown in FIG. 2E, a flat inter-layer insulating film 41 is formed on the inter-layer insulating film 39, covering the GND wiring line 40b.
Further, as shown in FIG. 2F, contact holes 42 and contact holes 43 are formed to expose the diffusion layers 37 serving as the source and drain of the n-channel channel MOSFET and the diffusion layers 38 serving as the source and drain of the p-channel MOSFET. Then, as shown in FIG. 2G, a p-type impurity is ion-implanted to the diffusion layers 37 and 38 to form p-type impurity doped layers 44 and p-type highly-concentrated impurity doped layers 45. Subsequently, as shown in FIG. 2H, an n-type impurity is ion-implanted to the diffusion layers 37 constituting the source and drain of the n-channel MOSFET to form n-type highly-concentrated impurity doped layers 44a while the p-channel MOSFET forming region which includes the contact holes 43 being covered with a resist pattern 46.
In formation of the source and drain wiring lines to be connected to the source and drain, the highly-concentrated impurity doped layers 44a and 45 are effective to decrease contact resistance between the electrode wiring line and each of the diffusion layers 37 and contact resistance between the electrode wiring line and each of the diffusion layers 38.
As described above, by forming the GND wiring line and the source and drain wiring line from different layers, that is, by providing a multi-layer wiring structure, the electrode wiring line can be drawn around with a margin and the integration degree can more be improved.
In the aforementioned conventional method, however, the impurities of the different conductivity types are doped in the predetermined regions in course of the impurity doping for decreasing the contact resistance between each of the source and drain layers and the electrode wiring layer and consequently, the number of production process steps is disadvantageously increased.
More particularly, while the n-type impurity is doped, the region where the p-type impurity has been doped must be masked with the resist pattern and accordingly, a process step which includes lithography is needed for formation of the resist pattern.
Therefore, when impurities of different conductivity types are doped in predetermined regions, respectively, the production process is inevitably prolonged.